1. Field of the Invention
The present invention relates to an insulated-gate type device driving circuit. Particularly, it relates to an insulated-gate type device driving circuit which can prevent an insulated-gate type device from being turned ON by mistake and which can perform an operation to turn OFF the insulated-gate type device at a high speed.
2. Description of the Background Art
As an insulated-gate type device driving circuit according to the background art, proposed is a configuration in which a current source circuit is provided, for example, to discharge a gate capacitance of a semiconductor switch element in order to turn OFF a current flowing into a main terminal of the semiconductor switch element, and a current regulation circuit is further provided to gradually decrease a current value for discharging the gate capacitance in accordance with the increase of a voltage between opposite ends of the main terminal of the semiconductor switch element so that both a surge voltage and a turn-OFF loss can be reduced (for example, see JP-A-2008-67593).
However, no measure against sudden increase in power supply when a power MOSFET is in an OFF state has been taken in the background-art example described in JP-A-2008-67593. Therefore, in such a situation, the power MOSFET which is in an OFF state may be turned ON by mistake due to a current flowing into a gate of the power MOSFET through a parasitic capacitance between the gate and a drain of the power MOSFET. In order to cope with this problem, it is necessary to keep an output current of the current source circuit at a predetermined current value or higher whenever the power MOSFET is turned OFF.
Since a voltage applied to the gate terminal is pulled down in this case, there arises a problem that the gate voltage of the power MOSFET in a normal ON state is decreased to cause decrease in the current conduction capacity of the power MOSFET (increase in Ron) or increase in current consumption.
In order to solve the problem of the background-art example described in JP-A-2008-67593, the present applicant has proposed a configuration shown in JP-A-2012-34079.
That is, in a background-art example described in JP-A-2012-34079, a semiconductor integrated circuit device 1 as a load drive control element is connected to one end of a load 3 such as a resistance load or an inductive load, while the other end of the load 3 is connected to a power supply 2, as shown in FIG. 12.
Input/output terminals of the semiconductor integrated circuit device 1 to the outside include three terminals, i.e. a drain terminal 4, a gate terminal 5 and a source terminal 6. The drain terminal 4 is connected to the one end of the load 3. The source terminal 6 is connected to the ground. In addition, a gate signal is inputted to the gate terminal 5 from the outside. The semiconductor integrated circuit device 1 is constituted by a drive circuit portion 17 and a power portion 18. The power portion 18 includes a power MOSFET (insulated-gate semiconductor element) 8 which is controllably turned ON/OFF by the drive circuit portion 17.
A Zener diode 9 is connected between the gate terminal 5 of the semiconductor integrated circuit device 1 and a ground potential (source potential) 24.
In addition, a current detecting sensor 10 is connected between a drain potential 22 and the ground potential 24. Further, a logic circuit (threshold control circuit) 12 is connected between the gate terminal 5 and the ground potential 24. A temperature detecting sensor 11 is connected between the logic circuit 12 and the ground potential 24.
As shown in FIG. 12, the logic circuit 12 has an N-type depletion MOSFET 12x, a diode 12y and an N-type enhancement MOSFET 12z. Further, a gate resistor 13 is connected between a gate of a power MOSFET 8 and the gate terminal 5.
Further, a p NMOSFET (gate voltage control semiconductor element) 14 is connected between a gate potential 23 and the ground potential 24 of the power MOSFET (insulated-gate semiconductor element) 8. An N-type depletion MOSFET 25 is connected as a pull-up element between a drain and a gate of the gate voltage control NMOSFET 14.
In addition, a gate voltage control circuit 15 is connected between the gate potential 23 and the ground potential 24. An input terminal of the gate voltage control circuit 15 is connected to an output terminal of the current detecting sensor 10.
Further, a constant current source 16 is connected between the gate potential 23 and the ground potential 24. This constant current source 16 is provided to pull down the gate potential 23 in order to prevent the power MOSFET 8 from being turned ON due to noise going into the gate terminal 5.
With the configuration made thus, a current supplied through a parasitic capacitance between the gate and a drain of the insulated-gate semiconductor element 8 is used as a power source to turn ON the gate voltage control semiconductor element 14. Accordingly, the charging current can be rapidly extracted by the gate voltage control semiconductor element 14 without depending on the output impedance of an input circuit applying a voltage to the gate terminal 5 or the OFF-time voltage level of a signal applied to the gate terminal 5. Accordingly, it is possible to prevent the insulated-gate semiconductor element from being turned ON by mistake and it is possible to turn OFF the insulated-gate semiconductor element at a high speed.
In the background-art example described in JP-A-2012-34079, the pull-up element 25 is provided between the gate and the drain of the gate voltage control NMOSFET 14 so that it is possible to prevent the insulated-gate semiconductor element from being turned ON by mistake and it is possible to turn OFF the insulated-gate semiconductor element at a high speed.
However, in the background-art example described in JP-A-2012-34079, the depletion-type MOSFET is used as the pull-up element. A back gate terminal of the depletion-type MOSFET is connected to a source terminal of the same MOSFET.
It will go well in the case where, of the elements constituting the semiconductor integrated circuit device 1, the N-type depletion MOSFET 25 and the depletion MOSFET 12x are constituted by individual (discrete) semiconductors separately, but there may arise a problem when these depletion MOSFETs are to be formed in the same semiconductor substrate as the other constituent elements of the semiconductor integrated circuit device 1. That is, consider that the power MOSFET (insulated-gate semiconductor element) 8, the gate voltage control NMOSFET (gate voltage control semiconductor element) 14, the N-type depletion MOSFET 25 as the pull-up element, and the N-type enhancement MOSFET 12z constituting the logic circuit (threshold control circuit) 12 are formed in one and the same N-type substrate. In this case, the insulated-gate semiconductor element 8 may be formed as a vertical type in an N-type substrate 100, the gate voltage control NMOSFET (gate voltage control semiconductor element) 14 and the N-type enhancement MOSFET 12z constituting the logic circuit 12 may be formed in a common p-type region (p-well) 101 and the pull-up element 25 constituted by the depletion-type MOSFET may be formed in an independent p-type region (p-well) 102 formed at a predetermined distance from the common p-type region (p-well) 101, as shown in FIG. 13.
With the configuration made thus, a parasitic PNP-type transistor is formed among the common p-type region 101, the independent p-type region 102 and the N-type substrate 100. For this reason, there is a possibility that the parasitic PNP-type transistor may operate to change the independent p-type region 102 into the ground potential when the power MOSFET (insulated-gate semiconductor element) 8 is turned ON to decrease the potential of the N-type substrate 100. In addition, when the potential of the N-type substrate 100 is low, electric charges in a source electrode (directly connected to the p-well region 102 by wiring) of the depletion-type MOSFET 25 constituting the pull-up element leak to the N-type substrate 100 through a PN-junction formed between the independent p-well region 102 and the N-type substrate 100. Thus, there may arise a problem that the gate voltage control semiconductor element cannot be pulled up excellently.